Bit lines of a memory cell array, for example, are connected to sense amplifiers via transistors in semiconductor devices such as NAND nonvolatile semiconductor memory devices. As the pitch of the bit lines is reduced, the pitch of the transistors also is reduced; and the contact portions connecting the bit lines to the transistors also are reduced. In the case where the contact portions are reduced, the junction breakdown voltage, for example, decreases; and the reliability deteriorates.
JP-A 2007-234878 (Kokai) discusses technology in which an impurity region that sets a threshold voltage is formed in the transistor region and the occupied surface area of the region where the transistors are formed is reduced. There is room for improvement to ensure high reliability while reducing the occupied surface area and reducing the chip surface area.